linux-kernel - Re: [PATCH RFC 0/4] mtd/spi-mem: Enable DQS support

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Message-ID: <41f49187-e68b-4731-ac86-7c346de63173@ti.com>
Date: Sat, 7 Feb 2026 01:02:12 +0530
From: Santhosh Kumar K <s-k6@...com>
To: Miquel Raynal <miquel.raynal@...tlin.com>, Mark Brown
	<broonie@...nel.org>, Richard Weinberger <richard@....at>, "Vignesh
 Raghavendra" <vigneshr@...com>
CC: Thomas Petazzoni <thomas.petazzoni@...tlin.com>, <praneeth@...com>,
	<u-kumar1@...com>, <p-mantena@...com>, <a-dutta@...com>,
	<linux-spi@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-mtd@...ts.infradead.org>, <s-k6@...com>
Subject: Re: [PATCH RFC 0/4] mtd/spi-mem: Enable DQS support

Hello Miquel,

On 06/02/26 00:36, Miquel Raynal wrote:
> For his PHY tuning series on the Cadence QSPI controller embedded in TI
> SoCs, Santhosh needs to access the availability of the DQS (data strobe)
> signal. This is a chip dependent capability, which may sometimes be
> enabled.
> 
> Create a SPI memory flag for it, let the SPI NAND core set this flag
> when it knows about the capability, and show how to use it from a SPI
> controller driver.
> 
> This is an alternative at needing a DT property. Please note that there
> are a few blind spots:
> - the line may not be wired (this would be surprising, but can be
>    flagged this time by a DT property)
> - manufacturer drivers must enable the feature if it is
>    available (especially for high speed DTR modes)
> - this implementation is proposed for SPI NANDs only, if this proposal
>    is accepted the same approach must be taken in SPI NOR.

Thank you for the series!

As mentioned in the tuning series, in addition to the flash advertising
its DQS capability, we also need a DT property to describe whether DQS
is physically connected to the controller. This can be represented using
either a "dqs-wired" or "dqs-not-wired" property; the exact naming can
be chosen based on the majority case.

With this series, the controller will enable or disable DQS by logically
AND-ing both pieces of information.

Regards,
Santhosh.

> 
> Here is the original thread which lead to this series:
> https://lore.kernel.org/linux-spi/87v7gbdwdh.fsf@bootlin.com/T/#ma79fc364d7b882a48dbdf47203dde75df4bb0ec4
> 
> This series was compile tested only at this stage. As DDR tuning does
> not yet work on my board, I cannot make sure this change has a real
> impact.
> 
> Signed-off-by: Miquel Raynal <miquel.raynal@...tlin.com>
> ---
> Miquel Raynal (4):
>        spi: spi-mem: Flag DQS capability
>        mtd: spi-nand: Set the DQS spi-mem capability if available
>        mtd: spi-nand: winbond: Enable the DQS pin on W35N**JW series
>        [DO NOT MERGE] spi: cadence-qspi: Retrieve DQS capability using the core helper
> 
>   drivers/mtd/nand/spi/core.c       |  4 ++++
>   drivers/mtd/nand/spi/winbond.c    |  8 ++++----
>   drivers/spi/spi-cadence-quadspi.c |  8 ++++++--
>   drivers/spi/spi-mem.c             | 32 ++++++++++++++++++++++++++++++++
>   include/linux/mtd/spinand.h       |  1 +
>   include/linux/spi/spi-mem.h       |  4 ++++
>   6 files changed, 51 insertions(+), 6 deletions(-)
> ---
> base-commit: c5884449d02575c7984000eb30d2a2971c7dfcc7
> change-id: 20260205-winbond-nand-next-phy-tuning-aabefc018032
> 
> Best regards,