lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <871pira46d.ffs@tglx>
Date: Wed, 11 Feb 2026 12:51:54 +0100
From: Thomas Gleixner <tglx@...nel.org>
To: Icenowy Zheng <zhengxingda@...as.ac.cn>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
 Huacai Chen <chenhuacai@...nel.org>, Jiaxun Yang <jiaxun.yang@...goat.com>
Cc: Yao Zi <me@...ao.cc>, linux-kernel@...r.kernel.org,
 devicetree@...r.kernel.org, linux-mips@...r.kernel.org, Icenowy Zheng
 <zhengxingda@...as.ac.cn>, linux-s390@...r.kernel.org, Heiko Carstens
 <hca@...ux.ibm.com>, Vasily Gorbik <gor@...ux.ibm.com>, Alexander Gordeev
 <agordeev@...ux.ibm.com>
Subject: Re: [PATCH v2 1/7] genirq: reserve NR_IRQS_LEGACY IRQs in dynirq by
 default

On Wed, Feb 11 2026 at 17:44, Icenowy Zheng wrote:
> Several architectures define NR_IRQS_LEGACY to reserve a low range of IRQ
> numbers for fixed legacy allocations (e.g. ISA interrupts) which should
> not be handed out by the dynamic IRQ allocator.
>
> arch_dynirq_lower_bound() exists to enforce this, but today only x86 wires
> it up. In the current boot order this typically works because legacy IRQ
> domains register early and claim the low IRQ numbers first; however, that
> assumption breaks if the legacy controller is probed later.
>
> Make the default arch_dynirq_lower_bound() implementation honour
> NR_IRQS_LEGACY by clamping the allocation start to at least that value.
>
> Architectures that do not define NR_IRQS_LEGACY keep the current behaviour
> (effectively 0). Arm/PowerPC/MIPS/LoongArch use legacy IRQ domains for ISA
> interrupts and benefit from this change. x86 and s390 already provide their
> own implementations.

Q: How do all those architectures which do not require the reservation
   of the legacy interrupts benefit from that?

A: Not at all

   - PowerPC has its own way to deal with that depending on the platform
     the kernel runs on as not all platforms require it despite it being
     defined.

   - ARM only uses it when SPARSE_IRQ=n and does not need it
     otherwise. So again this changes behaviour.

   - MIPS is only using it for mips/longsoon64 and the rest of MIPS does not
     care at all.

So if you need that on loonson, implement arch_dynirq_lower_bound()
instead of making uniformed claims.

Thanks,

        tglx

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ