linux-kernel - Re: [PATCH v2 1/4] arm64: dts: rockchip: use gated-fixed-clock for pcie-refclk on rk3588-jaguar

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Message-ID: <35e97a41-b88b-f526-351f-d4c5f70ee4e9@rock-chips.com>
Date: Wed, 11 Feb 2026 22:20:34 +0800
From: Shawn Lin <shawn.lin@...k-chips.com>
To: Heiko Stuebner <heiko@...ech.de>
Cc: shawn.lin@...k-chips.com, quentin.schulz@...rry.de,
 linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
 linux-kernel@...r.kernel.org, Heiko Stuebner <heiko.stuebner@...rry.de>
Subject: Re: [PATCH v2 1/4] arm64: dts: rockchip: use gated-fixed-clock for
 pcie-refclk on rk3588-jaguar

Hi Heiko

在 2026/02/10 星期二 16:02, Heiko Stuebner 写道:
> From: Heiko Stuebner <heiko.stuebner@...rry.de>
> 
> Using a combination of fixed clock and gpio-gate clock works but does
> not describe the actual hardware. Use the gated-fixed-clock binding
> to describe this in a nicer way.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@...rry.de>
> ---
>   .../arm64/boot/dts/rockchip/rk3588-jaguar.dts | 19 +++++--------------
>   1 file changed, 5 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
> index 952affaf455c..e21ad7575cb6 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
> @@ -86,25 +86,16 @@ led-1 {
>   		};
>   	};
>   
> -	/*
> -	 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
> -	 * clock generator.
> -	 * The clock output is gated via the OE pin on the clock generator.
> -	 * This is modeled as a fixed-clock plus a gpio-gate-clock.
> -	 */
> -	pcie_refclk_gen: pcie-refclk-gen-clock {
> -		compatible = "fixed-clock";
> +	/* 100MHz PCIe reference clock from PI6C557-05BLE */
> +	pcie_refclk: pcie-clock-generator {
> +		compatible = "gated-fixed-clock";
>   		#clock-cells = <0>;
>   		clock-frequency = <100000000>;
> -	};
> -
> -	pcie_refclk: pcie-refclk-clock {
> -		compatible = "gpio-gate-clock";
> -		clocks = <&pcie_refclk_gen>;
> -		#clock-cells = <0>;
> +		clock-output-names = "pcie-refclk-clock";
>   		enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */
>   		pinctrl-names = "default";
>   		pinctrl-0 = <&pcie30x4_clkreqn_m0>;

This looks fine,

Reviewed-by: Shawn Lin <shawn.lin@...k-chips.com>


> +		vdd-supply = <&vcca_3v3_s0>;
>   	};
>   
>   	pps {
>