linux-kernel - Re: [PATCH v2 2/4] arm64: dts: rockchip: use gated-fixed-clock for pcie-refclk on rk3588-tiger

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <e82bd097-3f66-ea31-9dce-77e806174763@rock-chips.com>
Date: Wed, 11 Feb 2026 22:24:49 +0800
From: Shawn Lin <shawn.lin@...k-chips.com>
To: Heiko Stuebner <heiko@...ech.de>
Cc: shawn.lin@...k-chips.com, quentin.schulz@...rry.de,
 linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
 linux-kernel@...r.kernel.org, Heiko Stuebner <heiko.stuebner@...rry.de>
Subject: Re: [PATCH v2 2/4] arm64: dts: rockchip: use gated-fixed-clock for
 pcie-refclk on rk3588-tiger

在 2026/02/10 星期二 16:03, Heiko Stuebner 写道:
> From: Heiko Stuebner <heiko.stuebner@...rry.de>
> 
> Using a combination of fixed clock and gpio-gate clock works but does
> not describe the actual hardware. Use the gated-fixed-clock binding
> to describe this in a nicer way.
> 
> Signed-off-by: Heiko Stuebner <heiko.stuebner@...rry.de>
> ---
>   .../arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 19 +++++--------------
>   1 file changed, 5 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
> index 27269b7b08aa..b4b8f305935f 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
> @@ -47,23 +47,14 @@ led-1 {
>   		};
>   	};
>   
> -	/*
> -	 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
> -	 * clock generator.
> -	 * The clock output is gated via the OE pin on the clock generator.
> -	 * This is modeled as a fixed-clock plus a gpio-gate-clock.
> -	 */
> -	pcie_refclk_gen: pcie-refclk-gen-clock {
> -		compatible = "fixed-clock";
> +	/* 100MHz PCIe reference clock from PI6C557-05BLE */
> +	pcie_refclk: pcie-clock-generator {
> +		compatible = "gated-fixed-clock";
>   		#clock-cells = <0>;
>   		clock-frequency = <100000000>;
> -	};
> -
> -	pcie_refclk: pcie-refclk-clock {
> -		compatible = "gpio-gate-clock";
> -		clocks = <&pcie_refclk_gen>;
> -		#clock-cells = <0>;
> +		clock-output-names = "pcie-refclk-clock";
>   		enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */

The change itself looks fine , so
Reviewed-by: Shawn Lin <shawn.lin@...k-chips.com>

However, if it's designed as active high, I would say Tiger is against
the the PCIe spec about how L1 substate work. Perhaps you could check
PCIe spec v7.0, Figure 5-16 Example: L1.2 Waveforms Illustrating
Upstream Port Initiated Exit.. When in L1.2, clkreq# should be released
by both ends, and the pull-up register by whatevery way will make it
into high, and thus refclk is gated automatically.


> +		vdd-supply = <&vcca_3v3_s0>;
>   	};
>   
>   	vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
>