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Date:	Sat, 30 Jun 2007 07:43:20 -0700
From:	Arjan van de Ven <arjan@...radead.org>
To:	Jeff Garzik <jgarzik@...ox.com>
Cc:	Francois Romieu <romieu@...zoreil.com>, netdev@...r.kernel.org,
	Edward Hsu <edward_hsu@...ltek.com.tw>
Subject: Re: [PATCH 10/21] r8169: merge with version 6.001.00 of Realtek's
	r8169 driver

On Sat, 2007-06-30 at 05:47 -0400, Jeff Garzik wrote:
> Francois Romieu wrote:
> > Jeff Garzik <jgarzik@...ox.com> :
> >> Arjan van de Ven wrote:
> >>>> +	pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
> >>> can you create a pci_set_latency_timer() for this please?
> > [...]
> >>>> +	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
> >>>> +		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 
> >>>> 0x08);
> >>> and something for this as well?
> >> Why?  Nothing here seems generic to me.
> > 
> > I.e. no need for pci_set_latency_timer(struct pci_dev *dev, u8 latency)
> > neither pci_set_cache_line_size(struct pci_dev *dev, u8 size) ?
> 
> Yeah.  When it gets to be a one-line wrapper like that, I don't see much 
> additional value in pci_set_cache_line_size() over 
> pci_write_config_byte(,PCI_CACHE_LINE_SIZE,).


but it isn't really a one line wrapper, since pci_set_cacheline_size()
would need to compare against the "system" size as well, and reject if
you try to set it smaller than that size that's a datacorruption issue.


(which makes me wonder; is the driver trying to work around a hardware
bug, or around behavior of early linux kernels that didn't set the
cacheline size in pci_enable_mwi() ... )

-- 
if you want to mail me at work (you don't), use arjan (at) linux.intel.com
Test the interaction between Linux and your BIOS via http://www.linuxfirmwarekit.org

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