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Date:	Wed, 15 Aug 2007 22:13:49 +0200
From:	Segher Boessenkool <segher@...nel.crashing.org>
To:	paulmck@...ux.vnet.ibm.com
Cc:	heiko.carstens@...ibm.com, horms@...ge.net.au,
	linux-kernel@...r.kernel.org, rpjday@...dspring.com, ak@...e.de,
	netdev@...r.kernel.org, cfriesen@...tel.com,
	akpm@...ux-foundation.org, torvalds@...ux-foundation.org,
	Nick Piggin <nickpiggin@...oo.com.au>,
	linux-arch@...r.kernel.org, jesper.juhl@...il.com, zlynx@....org,
	schwidefsky@...ibm.com, Chris Snook <csnook@...hat.com>,
	davem@...emloft.net, wensong@...ux-vs.org, wjiang@...ilience.com,
	David Howells <dhowells@...hat.com>
Subject: Re: [PATCH 6/24] make atomic_read() behave consistently on frv

>>>>> Well if there is only one memory location involved, then smp_rmb()
>>>>> isn't
>>>>> going to really do anything anyway, so it would be incorrect to use
>>>>> it.
>>>>
>>>> rmb() orders *any* two reads; that includes two reads from the same
>>>> location.
>>>
>>> If the two reads are to the same location, all CPUs I am aware of
>>> will maintain the ordering without need for a memory barrier.
>>
>> That's true of course, although there is no real guarantee for that.
>
> A CPU that did not provide this property ("cache coherence") would be
> most emphatically reviled.

That doesn't have anything to do with coherency as far as I can see.

It's just about the order in which a CPU (speculatively) performs the 
loads
(which isn't necessarily the same as the order in which it executes the
corresponding instructions, even).

> So we are pretty safe assuming that CPUs
> will provide it.

Yeah, pretty safe.  I just don't like undocumented assumptions :-)


Segher

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