netdev - Re: [PATCH 6/24] make atomic_read() behave consistently on frv

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Message-ID: <20070815203836.GO9645@linux.vnet.ibm.com>
Date:	Wed, 15 Aug 2007 13:38:36 -0700
From:	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>
To:	Segher Boessenkool <segher@...nel.crashing.org>
Cc:	heiko.carstens@...ibm.com, horms@...ge.net.au,
	linux-kernel@...r.kernel.org, rpjday@...dspring.com, ak@...e.de,
	netdev@...r.kernel.org, cfriesen@...tel.com,
	akpm@...ux-foundation.org, torvalds@...ux-foundation.org,
	Nick Piggin <nickpiggin@...oo.com.au>,
	linux-arch@...r.kernel.org, jesper.juhl@...il.com, zlynx@....org,
	schwidefsky@...ibm.com, Chris Snook <csnook@...hat.com>,
	davem@...emloft.net, wensong@...ux-vs.org, wjiang@...ilience.com,
	David Howells <dhowells@...hat.com>
Subject: Re: [PATCH 6/24] make atomic_read() behave consistently on frv

On Wed, Aug 15, 2007 at 10:13:49PM +0200, Segher Boessenkool wrote:
> >>>>>Well if there is only one memory location involved, then smp_rmb()
> >>>>>isn't
> >>>>>going to really do anything anyway, so it would be incorrect to use
> >>>>>it.
> >>>>
> >>>>rmb() orders *any* two reads; that includes two reads from the same
> >>>>location.
> >>>
> >>>If the two reads are to the same location, all CPUs I am aware of
> >>>will maintain the ordering without need for a memory barrier.
> >>
> >>That's true of course, although there is no real guarantee for that.
> >
> >A CPU that did not provide this property ("cache coherence") would be
> >most emphatically reviled.
> 
> That doesn't have anything to do with coherency as far as I can see.
> 
> It's just about the order in which a CPU (speculatively) performs the 
> loads
> (which isn't necessarily the same as the order in which it executes the
> corresponding instructions, even).

Please check the definition of "cache coherence".

Summary: the CPU is indeed within its rights to execute loads and stores
to a single variable out of order, -but- only if it gets the same result
that it would have obtained by executing them in order.  Which means that
any reordering of accesses by a single CPU to a single variable will be
invisible to the software.

> >So we are pretty safe assuming that CPUs
> >will provide it.
> 
> Yeah, pretty safe.  I just don't like undocumented assumptions :-)

Can't help you there!  ;-)

							Thanx, Paul
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