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Date:	Wed, 12 Sep 2007 09:47:46 -0700
From:	"Mandeep Baines" <>
To:	"Stephen Hemminger" <>
Cc:	"James Chapman" <>,,
	"Bill Fink" <>,,,,
Subject: Re: RFC: possible NAPI improvements to reduce interrupt rates for low traffic rates

On 9/12/07, Stephen Hemminger <> wrote:
> But if you compare this to non-NAPI driver the same softirq
> overhead happens. The problem is that for many older devices disabling IRQ's
> require an expensive non-cached PCI access. Smarter, newer devices
> all use MSI which is pure edge triggered and with proper register
> usage, NAPI should be no worse than non-NAPI.

Why would disabling IRQ's be expensive on non-MSI PCI devices?
Wouldn't it just require a single MMIO write to clear the interrupt
mask of the device. These are write-buffered so the latency should be
minimal. As mentioned in Jamal's UKUUG paper, any MMIO reading could
be avoided by caching the interrupt mask.
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