netdev - Re: RFC: possible NAPI improvements to reduce interrupt rates for low traffic rates

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Message-Id: <20070912.235711.71114960.davem@davemloft.net>
Date:	Wed, 12 Sep 2007 23:57:11 -0700 (PDT)
From:	David Miller <davem@...emloft.net>
To:	mandeep.baines@...il.com
Cc:	shemminger@...ux-foundation.org, jchapman@...alix.com,
	hadi@...erus.ca, billfink@...dspring.com, netdev@...r.kernel.org,
	jeff@...zik.org, ossthema@...ibm.com
Subject: Re: RFC: possible NAPI improvements to reduce interrupt rates for
 low traffic rates

From: "Mandeep Baines" <mandeep.baines@...il.com>
Date: Wed, 12 Sep 2007 09:47:46 -0700

> Why would disabling IRQ's be expensive on non-MSI PCI devices?
> Wouldn't it just require a single MMIO write to clear the interrupt
> mask of the device.

MMIO's are the most expensive part of the whole interrupt
servicing routines and minimizing them is absolutely
crucial.

This is why many devices do things like report status purely
in memory data structures, automatically disable interrupts
on either MSI delivery or status register read, etc.

Often you will see the first MMIO access in the interrupt
handler at the top of the profiles.
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