netdev - Re: [PATCH] e100: Add missing dma sync for proper operation with non-coherent caches.

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Message-ID: <20080826224916.GB8838@linux-mips.org>
Date:	Tue, 26 Aug 2008 23:49:16 +0100
From:	Ralf Baechle <ralf@...ux-mips.org>
To:	David Daney <ddaney@...rex.com>
Cc:	e1000-devel@...ts.sourceforge.net, netdev@...r.kernel.org,
	linux-mips <linux-mips@...ux-mips.org>
Subject: Re: [PATCH] e100: Add missing dma sync for proper operation with
	non-coherent caches.

On Mon, Aug 25, 2008 at 11:55:12PM -0700, David Daney wrote:

> I am running the e100 driver on a MIPS 4KEc system (32 bit mips with
> non-coherent DMA).  There was a problem where received packets would
> get 'stuck' for several seconds at a time and then be released all at
> once.
> 
> The cause was that if an interrupt were received when no RX packets
> were available, the status for the receive buffer would be stuck in
> the cache, so when the next interrupt arrived the old status value was
> read (indicating no packets available) instead of the new value.
> 
> The fix is to call pci_dma_sync_single_for_device on the RX if the
> packet is not available to invalidate the cache so that at the next
> interrupt valid status is returned.
> 
> The driver currently calls pci_dma_sync_single_for_cpu before reading
> the status, and this is indeed needed for cases like the R10000 CPU
> where the cache can be polluted by speculative execution, but for most
> machines it is a nop.
> 
> The patch was tested on 2.6.17-rc4 on a MIPS 4KEc.
> 
> Signed-off-by: David Daney <ddaney@...rex.com>

Makes sense to me.

Reviewed-by: Ralf Baechle <ralf@...ux-mips.org>

  Ralf
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