lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <1221824281.3103.8.camel@achroite>
Date:	Fri, 19 Sep 2008 12:38:01 +0100
From:	Ben Hutchings <bhutchings@...arflare.com>
To:	David Miller <davem@...emloft.net>
Cc:	netdev@...r.kernel.org
Subject: Re: multiqueue interrupts...

On Thu, 2008-09-18 at 19:38 -0700, David Miller wrote:
[...]
> So on a multiqueue card with 2 RX queues and 2 TX queues we'd
> have names like:
> 
> 	eth0-rx-0
> 	eth0-rx-1
> 	eth0-tx-0
> 	eth0-tx-1
> 
> So let's make an effort to get this done right in 2.6.28 and meanwhile
> Arjan can add the irqbalanced code.

What about the case where an interrupt is shared between RX and TX
completions?  Our hardware is very flexible in this regard, but based on
performance testing prior to the introduction of TX multiqueue we
currently allocate multiple interrupts for RX completions and share the
first with TX completions.

Ben.

-- 
Ben Hutchings, Senior Software Engineer, Solarflare Communications
Not speaking for my employer; that's the marketing department's job.
They asked us to note that Solarflare product names are trademarked.

--
To unsubscribe from this list: send the line "unsubscribe netdev" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ