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Message-Id: <20090529.150928.239765896.davem@davemloft.net>
Date: Fri, 29 May 2009 15:09:28 -0700 (PDT)
From: David Miller <davem@...emloft.net>
To: vapier.adi@...il.com
Cc: Michael.Hennerich@...log.com, netdev@...r.kernel.org,
uclinux-dist-devel@...ckfin.uclinux.org
Subject: Re: [Uclinux-dist-devel] [PATCH 1/5] netdev: bfin_mac: Blackfin
EMAC interrupt may not be shared
From: Mike Frysinger <vapier.adi@...il.com>
Date: Fri, 29 May 2009 07:45:05 -0400
> On Fri, May 29, 2009 at 07:28, David Miller wrote:
>> From: Mike Frysinger <vapier.adi@...il.com>
>>> why implement extra over head in an interrupt handler to support an
>>> operating mode the hardware can never support.
>>
>> What overhead? It should be pretty easy to see if the device
>> is really indicating an interrupt or not :-)
>
> which would involve reading system mmrs which are clocked at the
> system frequency and thus make the core stall
And the core doesn't stall reading in these cache lines that the chip
has just DMA'd to?
I think you're throwing the baby out with the bath water :-)
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