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Message-ID: <8bd0f97a0905291513m780898e9j6bd4c0b3b9ae8528@mail.gmail.com>
Date:	Fri, 29 May 2009 18:13:02 -0400
From:	Mike Frysinger <vapier.adi@...il.com>
To:	David Miller <davem@...emloft.net>
Cc:	Michael.Hennerich@...log.com, netdev@...r.kernel.org,
	uclinux-dist-devel@...ckfin.uclinux.org
Subject: Re: [Uclinux-dist-devel] [PATCH 1/5] netdev: bfin_mac: Blackfin EMAC 
	interrupt may not be shared

On Fri, May 29, 2009 at 18:09, David Miller wrote:
> From: Mike Frysinger <vapier.adi@...il.com>
>> On Fri, May 29, 2009 at 07:28, David Miller wrote:
>>> From: Mike Frysinger <vapier.adi@...il.com>
>>>> why implement extra over head in an interrupt handler to support an
>>>> operating mode the hardware can never support.
>>>
>>> What overhead?  It should be pretty easy to see if the device
>>> is really indicating an interrupt or not :-)
>>
>> which would involve reading system mmrs which are clocked at the
>> system frequency and thus make the core stall
>
> And the core doesn't stall reading in these cache lines that the chip
> has just DMA'd to?

the difference is that one of these is required in order for anything
to get done and the other is always useless noise.  also, the Blackfin
core does do speculative data fetching on external memory, but not
MMRs, so the stalling due to the data cache line fills will be
mitigated unlike the useless MMR reads.
-mike
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