netdev - Re: [PATCH] forcedeth: updated phy errata

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Message-ID: <4AA11CE7.7050400@nvidia.com>
Date:	Fri, 04 Sep 2009 09:57:59 -0400
From:	Ayaz Abdulla <aabdulla@...dia.com>
To:	David Miller <davem@...emloft.net>
CC:	"manfred@...orfullife.com" <manfred@...orfullife.com>,
	"akpm@...l.org" <akpm@...l.org>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: Re: [PATCH] forcedeth: updated phy errata



David Miller wrote:
> From: Ayaz Abdulla <aabdulla@...dia.com>
> Date: Mon, 31 Aug 2009 19:08:37 -0400
> 
> 
>>This patch updates the special programming (and/or errata) needed in
>>order to setup the phy for various vendor models.
>>
>>The new models include:
>>Marvell E1116
>>Marvell E1111
>>Marvell E1011
>>Marvell E3016
>>Broadcom 9507
>>Broadcom AC131
>>Broadcom 50610
>>
>>Signed-off-by: Ayaz Abdulla <aabdulla@...dia.com>
> 
> 
> Please document what these individual bits mean which you
> are clearing, by using an individual define for each register
> bit to describe it's purpose, and then define the mask as
> a concatenation of these bits.
> 
> Having an opaque bitmask is not how to do this.

Unfortunately, the phy vendors don't want us exposing the meaning of 
their non-standard bits.


> 
> Thanks.
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