netdev - Re: [RFC] skb align patch

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Message-ID: <4AB71980.4020208@gmail.com>
Date:	Mon, 21 Sep 2009 08:13:20 +0200
From:	Eric Dumazet <eric.dumazet@...il.com>
To:	Stephen Hemminger <shemminger@...tta.com>
CC:	Jesse Brandeburg <jesse.brandeburg@...il.com>,
	Jesper Dangaard Brouer <hawk@...u.dk>, netdev@...r.kernel.org
Subject: Re: [RFC] skb align patch

Stephen Hemminger a écrit :
> Based on the Intel suggestion that PCI-express overhead is
> a significant cost.
> 
> Would people doing performance please measure the impact of
> changing SKB alignment (64 bit only).

I had this idea some time ago when I hit a limit on bnx2 adapter
(Giga bit link, BCM5708S), with small packets. pktgen was able
to send ~500 Mbps 'only', or 700kps if I remember well.
So I tried to align the pktgen build packet to a cache line,
it gave no difference at all, but it was on a 32 bit kernel.
(Thus my patch was for pktgen only, not a generic one as yours)

Could you elaborate why this change could be useful on 64bit ?

Thanks

> 
> 
> --- a/arch/x86/include/asm/system.h	2009-09-20 14:08:40.922346912 -0700
> +++ b/arch/x86/include/asm/system.h	2009-09-20 14:14:37.012371200 -0700
> @@ -455,4 +455,14 @@ static inline void rdtsc_barrier(void)
>  	alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
>  }
>  
> +#ifndef CONFIG_X86_32
> +/*
> + * DMA to unaligned address is more expensive than the the
> + * overhead of unaligned CPU access.
> + */
> +#define NET_IP_ALIGN	0
> +#define NET_SKB_PAD	L1_CACHE_BYTES
> +#endif
> +
> +
>  #endif /* _ASM_X86_SYSTEM_H */
> --

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