netdev - Re: [net-next-2.6 PATCH 2/5] ixgbe: Make descriptor ring allocations NUMA-aware

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Message-ID: <Pine.WNT.4.64.1001080034340.15300@ppwaskie-MOBL2.amr.corp.intel.com>
Date:	Fri, 8 Jan 2010 00:36:01 -0800 (Pacific Standard Time)
From:	"Waskiewicz Jr, Peter P" <peter.p.waskiewicz.jr@...el.com>
To:	David Miller <davem@...emloft.net>
cc:	"Waskiewicz Jr, Peter P" <peter.p.waskiewicz.jr@...el.com>,
	"Kirsher, Jeffrey T" <jeffrey.t.kirsher@...el.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"gospo@...hat.com" <gospo@...hat.com>
Subject: Re: [net-next-2.6 PATCH 2/5] ixgbe: Make descriptor ring allocations
 NUMA-aware

On Fri, 8 Jan 2010, David Miller wrote:

> From: "Waskiewicz Jr, Peter P" <peter.p.waskiewicz.jr@...el.com>
> Date: Fri, 8 Jan 2010 00:25:26 -0800 (Pacific Standard Time)
> 
> > In our hardware (82598 and 82599), the CPU field in the DCA registers is 8 
> > bits.
> > 
> > The reason I truncated this was to fit these values into the 
> > first cacheline of the struct.  I also didn't figure we'd see a system 
> > that would have 255 NUMA nodes before 10 GbE was something that was on the 
> > shelf collecting dust.  :-)
> 
> The X86 port supports 9 for "NODES_SHIFT", and up to 4096 cpus.
> 
> Even when !MAXSMP, the cpu limit is 512.
> 
> Don't make the type ungeneric just because some current piece of
> hardware has that limitation.  This is how subtle bugs slip into the
> tree, and it makes auditing for such bugs a nightmare.
> 
> Thanks.

Understood.  Let me see if I can shuffle things around in the struct to 
keep my cacheline packed, and not screw with the data type sizes.  I'll 
respin and have Jeff push a new patch once I get it sorted out.

Thanks for the review Dave,

-PJ
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