netdev - Re: [net-2.6 PATCH] e1000e: enable/disable ASPM L0s and L1 and ERT according to hardware errata

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Message-Id: <20100429.120416.184828647.davem@davemloft.net>
Date:	Thu, 29 Apr 2010 12:04:16 -0700 (PDT)
From:	David Miller <davem@...emloft.net>
To:	bruce.w.allan@...el.com
Cc:	anton@...ba.org, jeffrey.t.kirsher@...el.com,
	netdev@...r.kernel.org, gospo@...hat.com, mjg@...hat.com
Subject: Re: [net-2.6 PATCH] e1000e: enable/disable ASPM L0s and L1 and ERT
 according to hardware errata

From: "Allan, Bruce W" <bruce.w.allan@...el.com>
Date: Thu, 29 Apr 2010 10:19:56 -0700

> Your patch is probably the correct thing to do but I'm not all that
> familiar with the ppc64 architecture.  Would you please provide the
> output of 'lspci -t' and 'lspci -vvv -xxx'.

You're not guarenteed for there to be a pci_dev backing the top-level
host controller, at the very least.  Some platforms don't even implement
the PCI config space for the host controller, whilst on others access
to them is protected by the hypervisor.

So you can't go poking around the PCI host controller registers
unconditionally.

The same OOPS probably would happen on Sparc64 in some configurations
too.  Although all of my PCI-E slots do have PCI-E express switch port
nodes, so maybe it wouldn't trigger here.

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