netdev - RE: [net-2.6 PATCH] e1000e: enable/disable ASPM L0s and L1 and ERT according to hardware errata

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Message-ID: <8DD2590731AB5D4C9DBF71A877482A90622DE3C2@orsmsx509.amr.corp.intel.com>
Date:	Fri, 30 Apr 2010 12:27:02 -0700
From:	"Allan, Bruce W" <bruce.w.allan@...el.com>
To:	David Miller <davem@...emloft.net>
CC:	"anton@...ba.org" <anton@...ba.org>,
	"Kirsher, Jeffrey T" <jeffrey.t.kirsher@...el.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"gospo@...hat.com" <gospo@...hat.com>,
	"mjg@...hat.com" <mjg@...hat.com>
Subject: RE: [net-2.6 PATCH] e1000e: enable/disable ASPM L0s and L1 and ERT
 according to hardware errata

On Thursday, April 29, 2010 12:04 PM, David Miller wrote:
> From: "Allan, Bruce W" <bruce.w.allan@...el.com>
> Date: Thu, 29 Apr 2010 10:19:56 -0700
> 
>> Your patch is probably the correct thing to do but I'm not all that
>> familiar with the ppc64 architecture.  Would you please provide the
>> output of 'lspci -t' and 'lspci -vvv -xxx'.
> 
> You're not guarenteed for there to be a pci_dev backing the top-level
> host controller, at the very least.  Some platforms don't even
> implement the PCI config space for the host controller, whilst on
> others access to them is protected by the hypervisor.
> 
> So you can't go poking around the PCI host controller registers
> unconditionally.
> 
> The same OOPS probably would happen on Sparc64 in some configurations
> too.  Although all of my PCI-E slots do have PCI-E express switch port
> nodes, so maybe it wouldn't trigger here.

In that case, I agree with Anton's patch.

Reviewed-by: Bruce Allan <bruce.w.allan@...el.com>

Thanks,
Bruce.--
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