netdev - Re: [PATCH net-next 09/14] tg3: Improve small packet performance

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Date:	Wed, 4 Aug 2010 15:47:29 -0700
From:	"Michael Chan" <mchan@...adcom.com>
To:	"Anton Blanchard" <anton@...ba.org>
cc:	"Matthew Carlson" <mcarlson@...adcom.com>,
	"davem@...emloft.net" <davem@...emloft.net>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"andy@...yhouse.net" <andy@...yhouse.net>
Subject: Re: [PATCH net-next 09/14] tg3: Improve small packet
 performance

On Wed, 2010-08-04 at 15:27 -0700, Anton Blanchard wrote:
> Hi,
> 
> Just saw this go in:
>   
> >  static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
> >  {
> > -	smp_mb();
> > +	/* Tell compiler to fetch tx indices from memory. */
> > +	barrier();
> >  	return tnapi->tx_pending -
> >  	       ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
> >  }
> 
> Which worries me. Are we sure we don't need any ordering (eg smp_rmb)?
> A compiler barrier does nothing to ensure two loads are ordered.

We generally only get an estimate of the available tx ring size when we
call tg3_tx_avail(), so memory barriers are not generally needed.  We
put a compiler barrier there to make sure that the compiler will fetch
the tx_prod and tx_cons from memory to give us a better estimate.

In specific cases detailed in the patch description, we do need memory
barriers when we call netif_tx_stop_queue() and then check for the tx
ring.  We decided to put memory barriers exactly where they're needed
instead of inside tg3_tx_avail() which is an overkill.

Thanks.

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