netdev - Re: [PATCH net-next 09/14] tg3: Improve small packet performance

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Message-ID: <20100804224607.GA4881@mcarlson.broadcom.com>
Date:	Wed, 4 Aug 2010 15:46:07 -0700
From:	"Matt Carlson" <mcarlson@...adcom.com>
To:	"Anton Blanchard" <anton@...ba.org>
cc:	"Matthew Carlson" <mcarlson@...adcom.com>,
	"davem@...emloft.net" <davem@...emloft.net>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"andy@...yhouse.net" <andy@...yhouse.net>,
	"Michael Chan" <mchan@...adcom.com>
Subject: Re: [PATCH net-next 09/14] tg3: Improve small packet
 performance

On Wed, Aug 04, 2010 at 03:27:41PM -0700, Anton Blanchard wrote:
> 
> Hi,
> 
> Just saw this go in:
>   
> >  static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
> >  {
> > -	smp_mb();
> > +	/* Tell compiler to fetch tx indices from memory. */
> > +	barrier();
> >  	return tnapi->tx_pending -
> >  	       ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
> >  }
> 
> Which worries me. Are we sure we don't need any ordering (eg smp_rmb)?
> A compiler barrier does nothing to ensure two loads are ordered.
> 
> Anton

The compiler barrier makes sure the loads stay roughly in the same
location.  In the places where the ordering really matters, we have the
memory barrier inlined into the calling code.  In the rest of the
places, we can relax the ordering requirement because the final value is
just used as an estimate.

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