netdev - Re: [PATCH 1/1] r8169.c correct MSIEnable register offset

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Date:	Wed, 14 Dec 2011 22:37:13 +0100
From:	Francois Romieu <romieu@...zoreil.com>
To:	Su Kang Yin <cantona@...tona.no-ip.org>
Cc:	hayeswang <hayeswang@...ltek.com>, linux-kernel@...r.kernel.org,
	nic_swsd@...ltek.com, netdev@...r.kernel.org
Subject: Re: [PATCH 1/1] r8169.c correct MSIEnable register offset

Su Kang Yin <cantona@...tona.no-ip.org> :
> correct MSIEnable (bit 5) register to Config1 (offset 0x52) instead of
> Config2 (offset 0x53)

I wonder where the inspiration for the MSIEnable bit came from.
It looks like something was confused with the Message Control word
in PCI space.

Imho you can simply remove it altogether.

-- 
Ueimor
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