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Date:	Thu, 15 Dec 2011 01:43:59 -0500 (EST)
From:	David Miller <davem@...emloft.net>
To:	romieu@...zoreil.com
Cc:	cantona@...tona.no-ip.org, hayeswang@...ltek.com,
	linux-kernel@...r.kernel.org, nic_swsd@...ltek.com,
	netdev@...r.kernel.org
Subject: Re: [PATCH 1/1] r8169.c correct MSIEnable register offset

From: Francois Romieu <romieu@...zoreil.com>
Date: Wed, 14 Dec 2011 22:37:13 +0100

> Su Kang Yin <cantona@...tona.no-ip.org> :
>> correct MSIEnable (bit 5) register to Config1 (offset 0x52) instead of
>> Config2 (offset 0x53)
> 
> I wonder where the inspiration for the MSIEnable bit came from.
> It looks like something was confused with the Message Control word
> in PCI space.
> 
> Imho you can simply remove it altogether.

Someone should find out what the real situation is with this.

Maybe it mirrors the PCI config space setting and is read-only, maybe
not.  But it should be determined for sure before changing this. :-)

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