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Date:	Thu, 15 Dec 2011 16:34:34 +0800
From:	hayeswang <hayeswang@...ltek.com>
To:	'David Miller' <davem@...emloft.net>, <romieu@...zoreil.com>
CC:	<cantona@...tona.no-ip.org>, <linux-kernel@...r.kernel.org>,
	'nic_swsd' <nic_swsd@...ltek.com>, <netdev@...r.kernel.org>
Subject: RE: [PATCH 1/1] r8169.c correct MSIEnable register offset

 

> -----Original Message-----
> From: David Miller [mailto:davem@...emloft.net] 
> Sent: Thursday, December 15, 2011 2:44 PM
> To: romieu@...zoreil.com
> Cc: cantona@...tona.no-ip.org; Hayeswang; 
> linux-kernel@...r.kernel.org; nic_swsd; netdev@...r.kernel.org
> Subject: Re: [PATCH 1/1] r8169.c correct MSIEnable register offset
> 
> From: Francois Romieu <romieu@...zoreil.com>
> Date: Wed, 14 Dec 2011 22:37:13 +0100
> 
> > Su Kang Yin <cantona@...tona.no-ip.org> :
> >> correct MSIEnable (bit 5) register to Config1 (offset 
> 0x52) instead of
> >> Config2 (offset 0x53)
> > 

The bit 5 of config1 (0x52) is reserved. And the bit 5 of Config2 (0x53) is
MSIEnable only for 8169 controler series.

> > I wonder where the inspiration for the MSIEnable bit came from.
> > It looks like something was confused with the Message Control word
> > in PCI space.
> > 
> > Imho you can simply remove it altogether.
> 
> Someone should find out what the real situation is with this.
> 
> Maybe it mirrors the PCI config space setting and is read-only, maybe
> not.  But it should be determined for sure before changing this. :-)
> 

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