netdev - Re: [PATCH 2/3] x86_64: Define 128-bit memory-mapped I/O operations

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Message-ID: <1345647537.2709.0.camel@bwh-desktop.uk.solarflarecom.com>
Date:	Wed, 22 Aug 2012 15:58:57 +0100
From:	Ben Hutchings <bhutchings@...arflare.com>
To:	Benjamin LaHaise <bcrl@...ck.org>
CC:	Linus Torvalds <torvalds@...ux-foundation.org>,
	"H. Peter Anvin" <hpa@...or.com>,
	David Miller <davem@...emloft.net>, <tglx@...utronix.de>,
	<mingo@...hat.com>, <netdev@...r.kernel.org>,
	<linux-net-drivers@...arflare.com>, <x86@...nel.org>
Subject: Re: [PATCH 2/3] x86_64: Define 128-bit memory-mapped I/O operations

On Wed, 2012-08-22 at 10:30 -0400, Benjamin LaHaise wrote:
> On Wed, Aug 22, 2012 at 03:24:59PM +0100, Ben Hutchings wrote:
> > -#ifdef EFX_USE_QWORD_IO
> > +#if defined(EFX_USE_OWORD_IO)
> > +       _efx_writeo(efx, value->u128, reg);
> > +#elif defined(EFX_USE_QWORD_IO)
> >         _efx_writeq(efx, value->u64[0], reg + 0);
> >         _efx_writeq(efx, value->u64[1], reg + 8);
> >  #else
> 
> This looks like a perfect fit for write combining.  I have traces showing 
> that enabling write combining on MMIO does indeed generate a single PCIe 
> transaction on at least a couple of different current systems.  Why is 
> that not an option?

Because reordering, and see the comment at the top of this file.

Ben.

-- 
Ben Hutchings, Staff Engineer, Solarflare
Not speaking for my employer; that's the marketing department's job.
They asked us to note that Solarflare product names are trademarked.

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