netdev - Re: [PATCH 2/3] x86_64: Define 128-bit memory-mapped I/O operations

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Message-ID: <1345653844.2709.51.camel@bwh-desktop.uk.solarflarecom.com>
Date:	Wed, 22 Aug 2012 17:44:04 +0100
From:	Ben Hutchings <bhutchings@...arflare.com>
To:	"H. Peter Anvin" <hpa@...or.com>
CC:	David Laight <David.Laight@...LAB.COM>,
	Benjamin LaHaise <bcrl@...ck.org>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	David Miller <davem@...emloft.net>, <tglx@...utronix.de>,
	<mingo@...hat.com>, <netdev@...r.kernel.org>,
	<linux-net-drivers@...arflare.com>, <x86@...nel.org>
Subject: Re: [PATCH 2/3] x86_64: Define 128-bit memory-mapped I/O operations

On Wed, 2012-08-22 at 08:54 -0700, H. Peter Anvin wrote:
> On 08/22/2012 08:51 AM, Ben Hutchings wrote:
> >>
> >> FWIW can you even guarantee to do an atomic 64bit PCIe transfer
> >> on many systems (without resorting to a dma unit).
> >
> > On any architecture that implements readq and writeq these had better be
> > atomic.
> >
> 
> Sorry, you fail.  There are definitely systems in the field where 
> readq() and writeq() are implemented, because the CPU supports them, 
> where the fabric does not guarantee they are intact.

Well, when the issue of 64-bit MMIO was discussed earlier this year, you
said nothing about this.  I thought the conclusion was that any
definitions provided by <asm/io.h> *must* be atomic and drivers can use
<asm-generic/io-64-nonatomic-hi-lo.h> or
<asm-generic/io-64-nonatomic-lo-hi.h> as a fallback.

Ben.

-- 
Ben Hutchings, Staff Engineer, Solarflare
Not speaking for my employer; that's the marketing department's job.
They asked us to note that Solarflare product names are trademarked.

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