netdev - Re: [PATCH v2] net/macb: fix ISR clear-on-write behavior only for some SoC

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Message-Id: <20130514.130450.144239429801008287.davem@davemloft.net>
Date:	Tue, 14 May 2013 13:04:50 -0700 (PDT)
From:	David Miller <davem@...emloft.net>
To:	plagnioj@...osoft.com
Cc:	nicolas.ferre@...el.com, hein_tibosch@...oo.es,
	michal.simek@...inx.com, ludovic.desroches@...el.com,
	s.trumtrar@...gutronix.de, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org, netdev@...r.kernel.org
Subject: Re: [PATCH v2] net/macb: fix ISR clear-on-write behavior only for
 some SoC

From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@...osoft.com>
Date: Tue, 14 May 2013 18:24:50 +0200

> On 15:00 Tue 14 May     , Nicolas Ferre wrote:
>> Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
>> introduces clear-on-write on ISR register. This behavior is not always
>> implemented when using Cadence MACB/GEM and is breaking other platforms.
>> We are using the Design Configuration Register 1 information and a capability
>> property to actually activate this clear-on-write behavior on ISR.
>> 
>> Reported-by: Hein Tibosch <hein_tibosch@...oo.es>
>> Signed-off-by: Nicolas Ferre <nicolas.ferre@...el.com>
> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@...osoft.com>

Applied, thanks.
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