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Message-ID: <CACna6rzgno_pQQkP018snvS7rKDgoNzaufx4WphEnOXhs53v0A@mail.gmail.com>
Date:	Fri, 3 Jan 2014 07:13:30 +0100
From:	Rafał Miłecki <zajec5@...il.com>
To:	Hauke Mehrtens <hauke@...ke-m.de>
Cc:	David Miller <davem@...emloft.net>,
	Network Development <netdev@...r.kernel.org>
Subject: Re: [PATCH 5/5] bgmac: add support for Northstar SoC (BCM4707, BCM53018)

2014/1/2 Hauke Mehrtens <hauke@...ke-m.de>:
> On 01/02/2014 09:40 PM, Rafał Miłecki wrote:
>>  > +       if (ci->id == BCMA_CHIP_ID_BCM4707 ||
>>> +           ci->id == BCMA_CHIP_ID_BCM53018) {
>>
>> Please add a missing
>> if (bgmac->phyaddr != BGMAC_PHY_NOREGS)
>> return;
>> at the beginning of this 4707/53018 block
>
> Why should I add that there?

This is what I can see in etcgmac.c version:
* $Id: etcgmac.c 414031 2013-07-23 10:54:51Z $


>>> +               bcma_awrite32(core, BCMA_IOCTL,
>>> +                             bcma_aread32(core, BCMA_IOCTL) | 0x44);
>>
>> Please use
>> BGMAC_BCMA_IOCTL_SW_CLKEN | 0x40
>> (unless you know 0x40, then replace it too).
>
> The Documentation says this is:
> * Bit 2 : TX_CLK_OUT_INVERT_EN - If set, this will invert the TX clock
> out of AMAC.
> And the other is:
> * Bit 12:8  "interface_mode"  This field is programmed through IDM
> control bits [6:2]
>
> see this:
> https://github.com/RMerl/asuswrt-merlin/blob/master/release/src-rt-6.x.4708/et/sys/etcgmac.c#L1039

Documentation is about "BCM4707 GMAC DevStatus register" which is:
#define BGMAC_DEV_CTL
That explains why you can't execute:
devstatus = R_REG(ch->osh, &regs->devstatus);
mode = ((devstatus & DS_MM_MASK) >> DS_MM_SHIFT);
code/path on BCM4707 family.

si_core_cflags -> ai_core_cflags operates on ai->ioctrl register (and
so does bcma_awrite32), so these documented bits don't apply to it.

-- 
Rafał
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