netdev - [PATCH 5/6] ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core

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Message-ID: <1398658225-25873-6-git-send-email-george.cherian@ti.com>
Date:	Mon, 28 Apr 2014 09:40:24 +0530
From:	George Cherian <george.cherian@...com>
To:	<netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<devicetree@...r.kernel.org>, <linux-omap@...r.kernel.org>
CC:	<davem@...emloft.net>, <richardcochran@...il.com>,
	<jeffrey.t.kirsher@...el.com>, <dborkman@...hat.com>,
	<ast@...mgrid.com>, <tklauser@...tanz.ch>, <mpa@...gutronix.de>,
	<bhutchings@...arflare.com>, <zonque@...il.com>, <balbi@...com>,
	<mugunthanvnm@...com>, <george.cherian@...com>, <t-kristo@...com>,
	<mturquette@...aro.org>, <linux@....linux.org.uk>,
	<galak@...eaurora.org>, <ijc+devicetree@...lion.org.uk>,
	<mark.rutland@....com>, <pawel.moll@....com>, <robh+dt@...nel.org>,
	<tony@...mide.com>, <bcousson@...libre.com>
Subject: [PATCH 5/6] ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk

cpsw_cpts_rft_clk has got the choice of 3 clocksources
 -dpll_core_m4_ck
 -dpll_core_m5_ck
 -dpll_disp_m2_ck

By default dpll_core_m4_ck is selected, witn this as clock
source the CPTS doesnot work properly. It gives clockcheck errors
while running PTP.

 clockcheck: clock jumped backward or running slower than expected!

By selecting dpll_core_m5_ck as the clocksource fixes this issue.
In AM335x dpll_core_m5_ck is the default clocksource.

Signed-off-by: George Cherian <george.cherian@...com>
---
 drivers/clk/ti/clk-43xx.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 67c8de5..b4877e0 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -110,9 +110,25 @@ static struct ti_dt_clk am43xx_clks[] = {
 
 int __init am43xx_dt_clk_init(void)
 {
+	struct clk *clk1, *clk2;
+
 	ti_dt_clocks_register(am43xx_clks);
 
 	omap2_clk_disable_autoidle_all();
 
+	/*
+	 * cpsw_cpts_rft_clk  has got the choice of 3 clocksources
+	 * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.
+	 * By default dpll_core_m4_ck is selected, witn this as clock
+	 * source the CPTS doesnot work properly. It gives clockcheck errors
+	 * while running PTP.
+	 * clockcheck: clock jumped backward or running slower than expected!
+	 * By selecting dpll_core_m5_ck as the clocksource fixes this issue.
+	 * In AM335x dpll_core_m5_ck is the default clocksource.
+	 */
+	clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk");
+	clk2 = clk_get_sys(NULL, "dpll_core_m5_ck");
+	clk_set_parent(clk1, clk2);
+
 	return 0;
 }
-- 
1.8.3.1

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