netdev - [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync

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Message-ID: <1398658225-25873-5-git-send-email-george.cherian@ti.com>
Date:	Mon, 28 Apr 2014 09:40:23 +0530
From:	George Cherian <george.cherian@...com>
To:	<netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<devicetree@...r.kernel.org>, <linux-omap@...r.kernel.org>
CC:	<davem@...emloft.net>, <richardcochran@...il.com>,
	<jeffrey.t.kirsher@...el.com>, <dborkman@...hat.com>,
	<ast@...mgrid.com>, <tklauser@...tanz.ch>, <mpa@...gutronix.de>,
	<bhutchings@...arflare.com>, <zonque@...il.com>, <balbi@...com>,
	<mugunthanvnm@...com>, <george.cherian@...com>, <t-kristo@...com>,
	<mturquette@...aro.org>, <linux@....linux.org.uk>,
	<galak@...eaurora.org>, <ijc+devicetree@...lion.org.uk>,
	<mark.rutland@....com>, <pawel.moll@....com>, <robh+dt@...nel.org>,
	<tony@...mide.com>, <bcousson@...libre.com>
Subject: [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync

Enable the Annex F Time Sync explicitly for DRA7x and AM4372.
With this enabled the L2 PTP is working.

while at that rename TS_BIT8 to TS_TTL_NONZERO

Signed-off-by: George Cherian <george.cherian@...com>
---
 drivers/net/ethernet/ti/cpsw.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 085ffb5..af1423b 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -248,7 +248,8 @@ struct cpsw_ss_regs {
 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
-#define TS_BIT8             (1<<8)  /* ts_ttl_nonzero? */
+#define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
+#define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
@@ -256,8 +257,9 @@ struct cpsw_ss_regs {
 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 
 #define CTRL_TS_BITS \
-	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
-	 TS_ANNEX_D_EN | TS_LTYPE1_EN)
+	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
+	 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
+	 TS_LTYPE1_EN)
 
 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
 #define CTRL_TX_TS_BITS  (CTRL_TS_BITS | TS_TX_EN)
-- 
1.8.3.1

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