netdev - RE: [PATCH] net: can: Remodel FlexCAN register read/write APIs for BE instances

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Message-ID: <063D6719AE5E284EB5DD2968C1650D6D17264BA8@AcuExch.aculab.com>
Date:	Wed, 25 Jun 2014 10:29:22 +0000
From:	David Laight <David.Laight@...LAB.COM>
To:	"'bhupesh.sharma@...escale.com'" <bhupesh.sharma@...escale.com>,
	"Marc Kleine-Budde" <mkl@...gutronix.de>,
	"linux-can@...r.kernel.org" <linux-can@...r.kernel.org>
CC:	"wg@...ndegger.com" <wg@...ndegger.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: RE: [PATCH] net: can: Remodel FlexCAN register read/write APIs for
 BE instances

From: bhupesh.sharma@...escale.com
> > From: Marc Kleine-Budde [mailto:mkl@...gutronix.de]
> > On 06/24/2014 05:54 PM, Bhupesh Sharma wrote:
> > > The FlexCAN IP on certain SoCs like (Freescale's LS1021A) is modelled
> > > in a big-endian fashion, i.e. the registers and the message buffers
> > > are organized in a BE way.
> >
> > Do you have any idea, why fsl did this? The messed up the network
> > controller on the mx28, too. :/
> 
> Not really. I guess s/w drivers are meant to hide h/w obscurities :)

I sometimes think they just like making life hard for software engineers.
It isn't as though 'gate count' is likely to be critical these days.

...
> Ok. Or should I create two functions for read and write - one does it in LE way and the other
> in BE way and parse the DT to understand which endianness the module supports.

An indirect call is likely to be slower than a conditional.
The conditional inside a non-inlined function is likely to get
predicted correctly on any code paths that matter.
Unfortunately using a real function increases register pressure.

Maybe a compile-time option for BE, LE or both.
So a 'generic' kernel can work, but a SoC specific one will be faster.
Then have the driver load/attach/init fail if it is the wrong endianness.

	David