netdev - Re: [PATCH net-next 1/3] ptp: Allow reassigning calibration pin function

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Message-ID: <CABkLOboZDJr8tr5JpaUijuNcJ7j7L8nMU33TC0WMn4iir-qVAw@mail.gmail.com>
Date:	Thu, 26 Jun 2014 08:14:58 +0200
From:	Christian Riesch <christian.riesch@...cron.at>
To:	Richard Cochran <richardcochran@...il.com>
Cc:	Stefan Sørensen <stefan.sorensen@...ctralink.com>,
	David Miller <davem@...emloft.net>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: Re: [PATCH net-next 1/3] ptp: Allow reassigning calibration pin function

Hi Richard,

On Thu, Jun 26, 2014 at 7:21 AM, Richard Cochran
<richardcochran@...il.com> wrote:
> On Wed, Jun 25, 2014 at 02:37:29PM +0200, Stefan Sørensen wrote:
>> The ptp pin function programming does not allow calibration pin to change
>> function. This is problematic on hardware that uses the default calibration
>> pin for other purposes.
>>
>> Removing this limitation does not impact calibration if userspace does not
>> reprogram the calibration pin.
>
> Reassigning the calibration function never makes sense, because it is
> only used in the driver probe method.

Yes, indeed, but isn't that a bug? I think the calibration should be
done again whenever the clock is loaded with a new value, i.e. in
ptp_dp83640_settime. See section 3.1 in [1]: "All subsequent settings
should use a step
adjustment or temporary rate adjustment, which should occur at each
PHY without introducing any error." This means, whenever we do
something else (directly write to the clock register), we must
recalibrate.

> Clobbering the calibration pin with another function only makes sense
> if the hardware design has exactly one PHY.

Or if the hardware has two PHYs that are not used at the same time. I
have a board that has two DP83640 on the same MII bus, one is used for
optical Ethernet, one for copper. Only one of the PHYs is powered up
at a time, the other one is in power down and MII isolate mode. In
such a case the calibration pin could be used for something else.

Christian
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