netdev - RE: [Patch net-next 08/11] net:fec: change FEC alignment to 64 bytes for ARM platform

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Message-ID: <e50c6383dc184566846e190026d1186a@BLUPR03MB373.namprd03.prod.outlook.com>
Date:	Thu, 4 Sep 2014 09:11:10 +0000
From:	"fugang.duan@...escale.com" <fugang.duan@...escale.com>
To:	David Laight <David.Laight@...LAB.COM>,
	"Frank.Li@...escale.com" <Frank.Li@...escale.com>,
	"davem@...emloft.net" <davem@...emloft.net>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"lznuaa@...il.com" <lznuaa@...il.com>
CC:	"shawn.guo@...aro.org" <shawn.guo@...aro.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: RE: [Patch net-next 08/11] net:fec: change FEC alignment to 64 bytes
 for ARM platform

From: David Laight <David.Laight@...LAB.COM> Sent: Thursday, September 04, 2014 4:51 PM
>To: Li Frank-B20596; Duan Fugang-B38611; davem@...emloft.net;
>netdev@...r.kernel.org; lznuaa@...il.com
>Cc: shawn.guo@...aro.org; linux-arm-kernel@...ts.infradead.org;
>devicetree@...r.kernel.org; Duan Fugang-B38611
>Subject: RE: [Patch net-next 08/11] net:fec: change FEC alignment to 64
>bytes for ARM platform
>
>From: Frank Li
>> From: Fugang Duan <B38611@...escale.com>
>>
>> Since enet-avb has 64 bytes alignment limitation for rx DMA transfer.
>> The previous enet IP for ARM platform has 16 bytes alignment for tx
>> DMA transfer.
>
>Do you mean rx or tx here? or both??
>
>And can we beat up the hardware designers to stop these restrictions on rx
>(in particular) ethernet buffer alignments?
>A device isn't suitable for ethernet unless is can write the destination
>mac address to a 4n+2 boundary.
>
>	David
>
Hi, David,

For previous enet IP there has 16 bytes data buffer alignment limitation for tx & rx DMA transfer.
For imx6sx enet-avb IP, there has 64 bytes data buffer alignment limitation for rx DMA transfer, byte alignment for tx data
Buffer for DMA transfer.

I think rx data buffer alignment limitation don't introduce performance drop, is not complex for sw implemention. Anyway,
We can request IC designer to remove the limitation for future chips.

Thanks,
Andy

>> 64 is the an integral number of 16, so change alignment to 64 bytes
>> for all ARM platform, which don't impact the performance of previous
>> platform.
>>
>> Signed-off-by: Fugang Duan <B38611@...escale.com>
>> Signed-off-by: Frank Li <Frank.Li@...escale.com>
>> ---
>>  drivers/net/ethernet/freescale/fec_main.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/ethernet/freescale/fec_main.c
>> b/drivers/net/ethernet/freescale/fec_main.c
>> index a232245..b388e29f 100644
>> --- a/drivers/net/ethernet/freescale/fec_main.c
>> +++ b/drivers/net/ethernet/freescale/fec_main.c
>> @@ -65,7 +65,7 @@
>>  static void set_multicast_list(struct net_device *ndev);
>>
>>  #if defined(CONFIG_ARM)
>> -#define FEC_ALIGNMENT	0xf
>> +#define FEC_ALIGNMENT	0x3f
>>  #else
>>  #define FEC_ALIGNMENT	0x3
>>  #endif
>> --
>> 1.9.1
>>
>> --
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