netdev - Re: [PATCH net-next 0/3] mlx4: CQE/EQE stride support

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Message-Id: <20140919.173208.77064865716362179.davem@davemloft.net>
Date:	Fri, 19 Sep 2014 17:32:08 -0400 (EDT)
From:	David Miller <davem@...emloft.net>
To:	ogerlitz@...lanox.com
Cc:	netdev@...r.kernel.org, amirv@...lanox.com, idos@...lanox.com
Subject: Re: [PATCH net-next 0/3] mlx4: CQE/EQE stride support

From: Or Gerlitz <ogerlitz@...lanox.com>
Date: Thu, 18 Sep 2014 11:50:58 +0300

> This series from Ido Shamay is intended for archs having 
> cache line larger then 64 bytes.
> 
> Since our CQE/EQEs are generally 64B in those systems, HW will write
> twice to the same cache line consecutively, causing pipe locks due to
> he hazard prevention mechanism. For elements in a cyclic buffer, writes
> are consecutive, so entries smaller than a cache line should be
> avoided, especially if they are written at a high rate.
> 
> Reduce consecutive writes to same cache line in CQs/EQs, by allowing the
> driver to increase the distance between entries so that each will reside
> in a different cache line.

Series applied, thanks.
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