netdev - Re: [patch net-next] mlxsw: pci: Adjust value of CPU egress traffic class

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Date:	Wed, 06 Jan 2016 00:49:25 -0500 (EST)
From:	David Miller <davem@...emloft.net>
To:	jiri@...nulli.us
Cc:	netdev@...r.kernel.org, idosch@...lanox.com, eladr@...lanox.com,
	yotamg@...lanox.com, ogerlitz@...lanox.com
Subject: Re: [patch net-next] mlxsw: pci: Adjust value of CPU egress
 traffic class

From: Jiri Pirko <jiri@...nulli.us>
Date: Tue,  5 Jan 2016 11:36:40 +0100

> From: Ido Schimmel <idosch@...lanox.com>
> 
> During initialization, when creating the send descriptor queues (SDQs),
> we specify the CPU egress traffic class of each SDQ. The maximum number
> of classes of this type is different in the two ASICs supported by this
> PCI driver.
> 
> New firmware versions check this value is set correctly, which causes
> errors on the Spectrum ASIC, as its max exposed egress traffic class is
> lower than 7.
> 
> Solve this by setting this field to 3, which is an acceptable value for
> both ASICs.
> 
> Note that we currently do not expose the QoS capabilities of the ASICs,
> so setting this to an hardcoded value is OK for now.
> 
> Signed-off-by: Ido Schimmel <idosch@...lanox.com>
> Signed-off-by: Jiri Pirko <jiri@...lanox.com>

Applied, thanks Jiri.
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