netdev - RE: [PATCH V2 5/5] i40e/ethtool: support coalesce setting by queue

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Message-ID: <FC41C24E35F18A40888AACA1A36F3E418AFE2A3B@fmsmsx115.amr.corp.intel.com>
Date:	Thu, 7 Jan 2016 22:25:58 +0000
From:	"Nelson, Shannon" <shannon.nelson@...el.com>
To:	"Liang, Kan" <kan.liang@...el.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"davem@...emloft.net" <davem@...emloft.net>,
	"bwh@...nel.org" <bwh@...nel.org>
CC:	"Brandeburg, Jesse" <jesse.brandeburg@...el.com>,
	"andi@...stfloor.org" <andi@...stfloor.org>,
	"f.fainelli@...il.com" <f.fainelli@...il.com>,
	"alexander.duyck@...il.com" <alexander.duyck@...il.com>,
	"Kirsher, Jeffrey T" <jeffrey.t.kirsher@...el.com>,
	"Wyborny, Carolyn" <carolyn.wyborny@...el.com>,
	"Skidmore, Donald C" <donald.c.skidmore@...el.com>,
	"Williams, Mitch A" <mitch.a.williams@...el.com>,
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	"ben@...adent.org.uk" <ben@...adent.org.uk>
Subject: RE: [PATCH V2 5/5] i40e/ethtool: support coalesce setting by queue

> -	for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
> -		u16 intrl = INTRL_USEC_TO_REG(vsi->int_rate_limit);
> +	if (queue < 0) {
> +		for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
> +			intrl = INTRL_USEC_TO_REG(vsi->int_rate_limit);
> +
> +			q_vector = vsi->q_vectors[i];
> +			q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
> +			wr32(hw, I40E_PFINT_ITRN(0, vector - 1), q_vector-
> >rx.itr);
> +			q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
> +			wr32(hw, I40E_PFINT_ITRN(1, vector - 1), q_vector-
> >tx.itr);

Use I40E_RX_ITR and I40E_TX_ITR rather than the hardcoded 0 and 1

> +			wr32(hw, I40E_PFINT_RATEN(vector - 1), intrl);
> +			i40e_flush(hw);
> +		}
> +	} else {
> +		if (queue >= vsi->num_queue_pairs) {
> +			netif_info(pf, drv, netdev, "Invalid queue value, queue
> range is 0 - %d\n", vsi->num_queue_pairs - 1);
> +			return -EINVAL;
> +		}
> +		intrl = INTRL_USEC_TO_REG(vsi->int_rate_limit);
> 
> -		q_vector = vsi->q_vectors[i];
> +		q_vector = vsi->rx_rings[queue]->q_vector;
> +		vector = vsi->base_vector + q_vector->v_idx;
>  		q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
>  		wr32(hw, I40E_PFINT_ITRN(0, vector - 1), q_vector->rx.itr);
> +
> +		q_vector = vsi->tx_rings[queue]->q_vector;
> +		vector = vsi->base_vector + q_vector->v_idx;
>  		q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
>  		wr32(hw, I40E_PFINT_ITRN(1, vector - 1), q_vector->tx.itr);

Of course, we should have had the I40E_RX_ITR and I40E_TX_ITR here to begin with.

This looks reasonable, but be aware that since there's no concept of queue-specific settings in the driver proper, these settings will get lost on the next reset - see i40e_vsi_configure_msix().  A reset can be driven by a number of things such as MTU changes, LLDP events, tx timeout recovery, promiscuous on/off, and various other configuration changes.  This might not be acceptable for your needs.

sln