lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CALzJLG_7bkC1nZix_SHD_OmumAm8vC-Bhjj6dD95QzNamLsstA@mail.gmail.com>
Date:	Wed, 17 Feb 2016 14:07:27 +0200
From:	Saeed Mahameed <saeedm@....mellanox.co.il>
To:	Or Gerlitz <gerlitz.or@...il.com>
Cc:	Saeed Mahameed <saeedm@...lanox.com>,
	"David S. Miller" <davem@...emloft.net>,
	Linux Netdev List <netdev@...r.kernel.org>,
	Tal Alon <talal@...lanox.com>,
	Eran Ben Elisha <eranbe@...lanox.com>,
	Tariq Toukan <tariqt@...lanox.com>
Subject: Re: [PATCH net-next 04/12] net/mlx5e: Support DCBNL IEEE ETS

On Tue, Feb 16, 2016 at 11:38 PM, Or Gerlitz <gerlitz.or@...il.com> wrote:
> On Tue, Feb 16, 2016 at 10:09 PM, Saeed Mahameed <saeedm@...lanox.com>
>> @@ -1602,7 +1622,7 @@ static int mlx5e_create_tis(struct mlx5e_priv
> *priv, int tc)
>>
>>         memset(in, 0, sizeof(in));
>>
>> -       MLX5_SET(tisc, tisc, prio,  tc);
>> +       MLX5_SET(tisc, tisc, prio, tc << 1);
>
> point bug fix? or we could never hit that prior to the patch as ## TCs
> was always 0?

tc was always 0 before this patch.

>
>>         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
>>
>>         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
>> @@ -1618,7 +1638,7 @@ static int mlx5e_create_tises(struct mlx5e_priv *priv)
>>         int err;
>>         int tc;
>>
>> -       for (tc = 0; tc < priv->params.num_tc; tc++) {
>> +       for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
>>                 err = mlx5e_create_tis(priv, tc);
>
> various places in the patch use priv->params.num_tc, wasn't sure if
> it's correct to hard code things here, and if it does, why not hard
> code everywhere
TISs and TIRs unlike SQs and RQs are created once on driver load, so
we create the MAX supported TISs (TIS per prio)  and when you create
the rings/channels (SQs) we create them according to the dynamic
"priv->params.num_tc" and then we assign the pre allocated TIS to the
SQ according to SQ TC/Prio configuration.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ