netdev - Re: [PATCH v5 net-next] net: Implement fast csum_partial for x86

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Message-ID: <CAKgT0UcQEkhbpBvT69tBKvmY1EVm91vMwVUHOdkE4RJ3hH+Q9g@mail.gmail.com>
Date:	Fri, 4 Mar 2016 16:15:00 -0800
From:	Alexander Duyck <alexander.duyck@...il.com>
To:	David Laight <David.Laight@...lab.com>
Cc:	Linus Torvalds <torvalds@...ux-foundation.org>,
	Tom Herbert <tom@...bertland.com>,
	"davem@...emloft.net" <davem@...emloft.net>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"tglx@...utronix.de" <tglx@...utronix.de>,
	"mingo@...hat.com" <mingo@...hat.com>,
	"hpa@...or.com" <hpa@...or.com>, "x86@...nel.org" <x86@...nel.org>,
	"kernel-team@...com" <kernel-team@...com>
Subject: Re: [PATCH v5 net-next] net: Implement fast csum_partial for x86_64

On Fri, Mar 4, 2016 at 2:38 AM, David Laight <David.Laight@...lab.com> wrote:
> From: Linus Torvalds
>> Sent: 03 March 2016 18:44
>>
>> On Thu, Mar 3, 2016 at 8:12 AM, David Laight <David.Laight@...lab.com> wrote:
>> >
>> > Did you try the asm loop that used 'leax %rcx..., jcxz... jmps..'
>> > without any unrolling?
>>
>> Is that actually supposed to work ok these days? jcxz used to be quite
>> slow, and is historically *never* used.
>>
>> Now, in theory, loop constructs can actually do better on branch
>> prediction etc, but Intel seems to have never really tried to push
>> them, and has instead pretty much discouraged them in favor of making
>> the normal jumps go faster (including all the instruction fusion etc)
>
> Yes, they've even added the 'adc using the overflow flag' but not made
> it possible to put that into a loop.
>
>> From what I have seen, the whole "don't use LOOP or JRCXZ" has not changed.
>
> LOOP is still slow on intel cpus (but is single clock on recentish amd ones).
>
> JCXZ is reasonable on most cpus, certainly all the ones we care about these days.
> On intel cpus JCXZ is still 2 clocks, but it removes the dependency on any
> flags (which all other conditional instructions have).
> The difficulty is using it for a loop (you need JCXNZ or a fast LOOP).
> An alternative to the 'JCXZ, JMPS' pair would be to move the high bits
> of the counter into the low bits of cx so that cx would become non-zero
> on the last iteration.

Actually probably the easiest way to go on x86 is to just replace the
use of len with (len >> 6) and use decl or incl instead of addl or
subl, and lea instead of addq for the buff address.  None of those
instructions effect the carry flag as this is how such loops were
intended to be implemented.

I've been doing a bit of testing and that seems to work without
needing the adcq until after you exit the loop, but doesn't give that
much of a gain in speed for dropping the instruction from the
hot-path.  I suspect we are probably memory bottle-necked already in
the loop so dropping an instruction or two doesn't gain you much.

- Alex