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Message-Id: <20160702.144924.2057687330898460203.davem@davemloft.net>
Date: Sat, 02 Jul 2016 14:49:24 -0400 (EDT)
From: David Miller <davem@...emloft.net>
To: stefan@...user.net
Cc: netdev@...r.kernel.org, f.fainelli@...il.com
Subject: Re: [PATCH] net: phy: dp83867: Fix initialization of PHYCR register
From: Stefan Hauser <stefan@...user.net>
Date: Fri, 1 Jul 2016 22:35:03 +0200
> When initializing the PHY control register, the FIFO depth bits are
> written without reading the previous register value, i.e. all other
> bits are overwritten with zero. This disables automatic MDI-X
> configuration, which is enabled by default. Fix initialization by doing
> a read/modify/write operation.
>
> Signed-off-by: Stefan Hauser <stefan@...user.net>
Applied.
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