netdev - Re: Alignment issues with freescale FEC driver

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Message-Id: <20160923.224553.1824171056324385383.davem@davemloft.net>
Date:   Fri, 23 Sep 2016 22:45:53 -0400 (EDT)
From:   David Miller <davem@...emloft.net>
To:     eric@...int.com
Cc:     andrew@...n.ch, edumazet@...gle.com, fugang.duan@....com,
        otavio@...ystems.com.br, netdev@...r.kernel.org,
        troy.kisky@...ndarydevices.com, rmk+kernel@....linux.org.uk,
        cjb.sw.nospam@...il.com, linux-arm-kernel@...ts.infradead.org
Subject: Re: Alignment issues with freescale FEC driver

From: Eric Nelson <eric@...int.com>
Date: Fri, 23 Sep 2016 11:35:17 -0700

> From the i.MX6DQ reference manual, bit 7 of ENET_RACC says this:
> 
> "RX FIFO Shift-16
> 
> When this field is set, the actual frame data starts at bit 16 of the first
> word read from the RX FIFO aligning the Ethernet payload on a
> 32-bit boundary."
> 
> Same for the i.MX6UL.
> 
> I'm not sure what it will take to use this, but it seems to be exactly
> what we're looking for.

+1