netdev - Re: [PATCH] MIPS: NI 169445 board support

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Date:   Wed, 4 Jan 2017 10:38:36 -0600
From:   Nathan Sullivan <nathan.sullivan@...com>
To:     Ralf Baechle <ralf@...ux-mips.org>, <linux-mips@...ux-mips.org>
CC:     <davem@...emloft.net>, <netdev@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] MIPS: NI 169445 board support

On Tue, Dec 20, 2016 at 05:34:34PM +0100, Ralf Baechle wrote:
> On Fri, Dec 02, 2016 at 09:42:09AM -0600, Nathan Sullivan wrote:
> > Date:   Fri, 2 Dec 2016 09:42:09 -0600
> > From: Nathan Sullivan <nathan.sullivan@...com>
> > To: ralf@...ux-mips.org, mark.rutland@....com, robh+dt@...nel.org
> > CC: linux-mips@...ux-mips.org, devicetree@...r.kernel.org,
> >  linux-kernel@...r.kernel.org, Nathan Sullivan <nathan.sullivan@...com>
> > Subject: [PATCH] MIPS: NI 169445 board support
> > Content-Type: text/plain
> > 
> > Support the National Instruments 169445 board.
> 
> Nathan,
> 
> I assume you're going to repost the changes Rob asked for in
> https://patchwork.linux-mips.org/patch/14641/#26924 and resubmit?
> 
> Thanks,
> 
>   Ralf

Hmm, I found the issue with the generic MIPS config and dwc_eth_qos.  The NIC
driver attempts to cache align a descriptor ring using the ___cacheline_aligned
attribute on the descriptor struct, in combination with a "skip" feature in
hardware.  However, the skip feature only has a three bit field, and the generic
MIPS config selects MIPS_L1_CACHE_SHIFT_7.  So, the line size is 128, and with a
64-bit bus, that means the NIC descriptor skip field would need to be set to
14 to align the 16-byte descriptors...

I guess it makes sense for a generic MIPS kernel to align everything for 128 byte
cache lines, and for me to fix the dwc_eth_qos driver to handle cases where the
line size is too big for the hardware skip feature, right?

Thanks,

   Nathan