netdev - Re: Disabling msix interrupts

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Message-Id: <20170206.141449.371774071782410941.davem@davemloft.net>
Date:   Mon, 06 Feb 2017 14:14:49 -0500 (EST)
From:   David Miller <davem@...emloft.net>
To:     David.Laight@...LAB.COM
Cc:     alexander.duyck@...il.com, netdev@...r.kernel.org,
        linux-pci@...r.kernel.org
Subject: Re: Disabling msix interrupts

From: David Laight <David.Laight@...LAB.COM>
Date: Mon, 6 Feb 2017 17:23:54 +0000

> Although the 'store buffer' on the sparc cpus I used to use would
> let reads overtake writes. So you did have to read back the address
> of the last write - not sure about modern sparc cpus.

Never would any sparc cpu do so when any of the operations involved
were to "side effect" locations, as PCI config space is.