netdev - RE: Disabling msix interrupts

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Message-ID: <063D6719AE5E284EB5DD2968C1650D6DB027DA37@AcuExch.aculab.com>
Date:   Tue, 7 Feb 2017 09:55:47 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'David Miller' <davem@...emloft.net>
CC:     "alexander.duyck@...il.com" <alexander.duyck@...il.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>
Subject: RE: Disabling msix interrupts

From: David Miller
> Sent: 06 February 2017 19:15
> From: David Laight <David.Laight@...LAB.COM>
> Date: Mon, 6 Feb 2017 17:23:54 +0000
> 
> > Although the 'store buffer' on the sparc cpus I used to use would
> > let reads overtake writes. So you did have to read back the address
> > of the last write - not sure about modern sparc cpus.
> 
> Never would any sparc cpu do so when any of the operations involved
> were to "side effect" locations, as PCI config space is.

I guess they used non-zero ASI, and that forced the flush??
Normal uncached memory reads would overtake writes.
(These were SuperSparc (Viking)).

	David