netdev - Re: Disabling msix interrupts

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Message-Id: <20170207.112645.492478528794181275.davem@davemloft.net>
Date:   Tue, 07 Feb 2017 11:26:45 -0500 (EST)
From:   David Miller <davem@...emloft.net>
To:     David.Laight@...LAB.COM
Cc:     alexander.duyck@...il.com, netdev@...r.kernel.org,
        linux-pci@...r.kernel.org
Subject: Re: Disabling msix interrupts

From: David Laight <David.Laight@...LAB.COM>
Date: Tue, 7 Feb 2017 09:55:47 +0000

> From: David Miller
>> Sent: 06 February 2017 19:15
>> From: David Laight <David.Laight@...LAB.COM>
>> Date: Mon, 6 Feb 2017 17:23:54 +0000
>> 
>> > Although the 'store buffer' on the sparc cpus I used to use would
>> > let reads overtake writes. So you did have to read back the address
>> > of the last write - not sure about modern sparc cpus.
>> 
>> Never would any sparc cpu do so when any of the operations involved
>> were to "side effect" locations, as PCI config space is.
> 
> I guess they used non-zero ASI, and that forced the flush??
> Normal uncached memory reads would overtake writes.
> (These were SuperSparc (Viking)).

On sun4m it was controlled by bits in the physical address.