netdev - Re: [PATCH net 1/4] pegasus: Use heap buffers for all register access

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Message-ID: <CAJJ6jxt-47saW=B260j0v_Gdt-dwb4YepRZTWQ-nYfLBGQUT=w@mail.gmail.com>
Date:   Tue, 7 Feb 2017 10:32:16 -0800
From:   Steve Calfee <stevecalfee@...il.com>
To:     Petko Manolov <petkan@...leusys.com>
Cc:     Greg KH <greg@...ah.com>, Ben Hutchings <ben@...adent.org.uk>,
        netdev@...r.kernel.org, USB list <linux-usb@...r.kernel.org>,
        Lisandro Damián Nicanor Pérez Meyer 
        <lisandro@...ian.org>
Subject: Re: [PATCH net 1/4] pegasus: Use heap buffers for all register access

On Mon, Feb 6, 2017 at 4:51 AM, Petko Manolov <petkan@...leusys.com> wrote:
> On 17-02-06 09:28:22, Greg KH wrote:
>> On Mon, Feb 06, 2017 at 10:14:44AM +0200, Petko Manolov wrote:
>> > On 17-02-05 01:30:39, Greg KH wrote:
>> > > On Sat, Feb 04, 2017 at 04:56:03PM +0000, Ben Hutchings wrote:
>> > > > Allocating USB buffers on the stack is not portable, and no longer works
>> > > > on x86_64 (with VMAP_STACK enabled as per default).
>> > >
>> > > It's never worked on other platforms, so these should go to the stable
>> > > releases please.
>> >
>> > As far as i know both drivers works fine on other platforms, though I only
>> > tested it on arm and mipsel. ;)
>>
>> It all depends on the arm and mips platforms, the ones that can not DMA from
>> stack memory are the ones that would always fail here (since the 2.2 kernel
>> days).
>
> Seems like most modern SOCs have decent DMA controllers.
>

The real problem is not DMA exactly, it is cache coherency.

X86 has a coherent cache and all the cpu cores watch DMA transfers and
keep the cpu caches up to date.

Most ARMs and MIPS processors have incoherent cache, so DMA can change
memory without the CPU cache updates. CPU cache view of what is in
memory can be different from what was DMAed in, this makes failures
very hard to detect, reproduce and racy.

So all DMA buffers should always be separate allocations from the
stack AND not be embedded in structs. Memory allocations are always at
least cache line aligned, so coherency is not a problem.

Regards, Steve