netdev - Re: stmmac still supporting spear600 ?

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Date:   Sun, 2 Apr 2017 23:30:28 +0200
From:   Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
To:     Giuseppe CAVALLARO <peppe.cavallaro@...com>
Cc:     Alexandre Torgue <alexandre.torgue@...com>,
        <netdev@...r.kernel.org>, Viresh Kumar <vireshk@...nel.org>,
        Shiraz Hashim <shiraz.linux.kernel@...il.com>,
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: stmmac still supporting spear600 ?

Hello,

On Thu, 23 Mar 2017 11:33:23 +0100, Giuseppe CAVALLARO wrote:

> > Further research has revealed that everything is working fine on a
> > platform with a Gigabit PHY connected via GMII.
> >
> > However, on a different platform (which I'm using) with a 10/100 PHY
> > connected via MII, DMA_RESET never clears, and networking doesn't work.
> > The SMSC PHY LAN8700 is also supposed to be providing the clock through
> > its TX_CLK pin. I double checked, and both the MAC and PHY are in MII
> > mode, but still no luck so far.
> >
> > Of course, if you have any suggestion or hint, I'm all ears :)  
> 
> I can just you to keep the focus on clock configuration. I tested the 
> SMSC PHY LAN8700
> w/o any issues on several platform.  In MII both rx/tx_clk are provided 
> by PHY and if you
> have an external oscillator this should be safe enough, indeed.
> Another check you can do is about the reset time! Maybe you need to 
> change something
> when reset the SMSC transceiver, try to increase the delay (if you use 
> GPIO to reset it).

On which platform did you test with the LAN8700 PHY ? Was it on a
SPEAr600 based platform ?

If you tested on SPEAr600, what is the GMAC clock configuration (i.e
the value of the GMAC_CFG_CTR and GMAC_CFG_SYNT registers) ?

Regarding the PHY reset time, our PHY reset pin is not connected to a
GPIO, but to the system reset logic, so Linux cannot reset the PHY with
a GPIO.

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com