netdev - Re: [PATCH] net: ethernet: stmmac: properly set PS bit in MII configurations during reset

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Message-ID: <20170515162734.187845dc@free-electrons.com>
Date:   Mon, 15 May 2017 16:27:34 +0200
From:   Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
To:     Giuseppe CAVALLARO <peppe.cavallaro@...com>
Cc:     Corentin Labbe <clabbe.montjoie@...il.com>,
        Alexandre Torgue <alexandre.torgue@...com>,
        <netdev@...r.kernel.org>, <stable@...r.kernel.org>
Subject: Re: [PATCH] net: ethernet: stmmac: properly set PS bit in MII
 configurations during reset

Hello Giuseppe,

On Wed, 10 May 2017 09:18:17 +0200, Thomas Petazzoni wrote:

> On Wed, 10 May 2017 09:03:12 +0200, Giuseppe CAVALLARO wrote:
> 
> > > Please, read again my patch and the description of the problem that I
> > > have sent. But basically, any solution that does not allow to set the
> > > PS bit between asserting the DMA reset bit and polling for it to clear
> > > will not work for MII PHYs.    
> > 
> > yes your point was clear to me, I was just wondering if we could find an 
> > easier way
> > to solve it w/o changing the API, adding  the set_ps and propagating the 
> > "interface"
> > inside the DMA reset.
> > 
> > Maybe this could be fixed in the glue-logic in some way. Let me know 
> > what do you think.  
> 
> Well, it's more up to you to tell me how you would like this be solved.
> We figured out what the problem was, but I don't know well enough the
> architecture of the driver to decide how the solution to this problem
> should be designed. I made an initial simple proposal to show what is
> needed, but I'm definitely open to suggestions.

Do you have any suggestion on how to move forward with this?

Thanks a lot,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com