netdev - Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

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Message-ID: <20171130181520.GF10595@n2100.armlinux.org.uk>
Date:   Thu, 30 Nov 2017 18:15:20 +0000
From:   Russell King - ARM Linux <linux@...linux.org.uk>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Bhaskar Upadhaya <bhaskar.upadhaya@....com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 1/1] phy: Add 2.5G SGMII interface mode

On Thu, Nov 30, 2017 at 06:41:27PM +0100, Andrew Lunn wrote:
> SGMII supports passing auto-negotiation results from the PHY to the
> MAC. 1000BASE-X does not.
> 
> SGMII supports the PHY running at 10, 100, and 1000 Mbps. But to
> support this, the MAC needs to replicate the bits 100, or 10 times
> when the PHY is running in 10 or 100Mbps mode.
> 
> So with your 2.5G SGMII, you need to replicate the bits 250, 25, or
> 2.5 times if they PHY is running at lower speeds. This last one is
> interesting.

That's not what I've read so far - but I don't know about the PHY
in this exact case because the docs are only available under NDA
(which makes it incredibly difficult to have this discussion.)

However, from what I can ascertain from a Xilinx document, 2.5G is
1G SGMII clocked 2.5x faster.  When in 2.5G mode, the other modes
are unavailable.  There's also no 250M or 25M as the speed bits
are not relevant.

The Xilinx doc does talk about a "2.5G SGMII standard" but I haven't
been able to locate such a thing - maybe someone can provide some
pointers?

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
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