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Message-Id: <20171205132600.13796-1-dev@g0hl1n.net>
Date: Tue, 5 Dec 2017 14:25:56 +0100
From: Richard Leitner <dev@...l1n.net>
To: robh+dt@...nel.org, mark.rutland@....com, fugang.duan@....com,
andrew@...n.ch, f.fainelli@...il.com, frowand.list@...il.com
Cc: davem@...emloft.net, geert+renesas@...der.be,
sergei.shtylyov@...entembedded.com, baruch@...s.co.il,
david.wu@...k-chips.com, lukma@...x.de, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
richard.leitner@...data.com
Subject: [PATCH net-next v3 0/4] net: fec: fix refclk enable for SMSC LAN8710/20
From: Richard Leitner <richard.leitner@...data.com>
This patch series fixes the use of the SMSC LAN8710/20 with a Freescale ETH
when the refclk is generated by the FSL.
This patch depends on the "phylib: Add device reset GPIO support" patch
submitted by Geert Uytterhoeven/Sergei Shtylyov, see:
https://patchwork.kernel.org/patch/10090149/
Changes v3:
- use phylib to hard-reset the PHY
- implement reset delays in phylib
- add new phylib API & flag (PHY_RST_AFTER_CLK_EN) to determine if a PHY
is affected
Changes v2:
- simplify and fix fec_reset_phy function to support multiple calls
- include: linux: phy: harmonize phy_id{,_mask} type
- reset the phy instead of not turning the clock on and off
(which would have caused a power consumption regression)
Richard Leitner (4):
phylib: Add device reset delay support
phylib: add reset after clk enable support
net: phy: smsc: LAN8710/20: add PHY_RST_AFTER_CLK_EN flag
net: fec: add phy_reset_after_clk_enable() support
Documentation/devicetree/bindings/net/phy.txt | 10 ++++++++++
drivers/net/ethernet/freescale/fec_main.c | 7 +++++++
drivers/net/phy/mdio_device.c | 13 +++++++++++--
drivers/net/phy/phy_device.c | 24 ++++++++++++++++++++++++
drivers/net/phy/smsc.c | 2 +-
drivers/of/of_mdio.c | 8 ++++++++
include/linux/mdio.h | 2 ++
include/linux/phy.h | 2 ++
8 files changed, 65 insertions(+), 3 deletions(-)
--
2.11.0
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