netdev - Re: [PATCH RFC 0/4] Fixes for Marvell MII paged register access races

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20171209190610.GC2299@lunn.ch>
Date:   Sat, 9 Dec 2017 20:06:10 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Florian Fainelli <f.fainelli@...il.com>
Cc:     Russell King - ARM Linux <linux@...linux.org.uk>,
        netdev@...r.kernel.org
Subject: Re: [PATCH RFC 0/4] Fixes for Marvell MII paged register access races

> > Another potential question is whether using the mdiobus lock (which
> > excludes all other MII bus access) is best - while it has the advantage
> > of also ensuring atomicity with userspace accesses, it means that no one
> > else can access an independent PHY on the same bus while a paged access
> > is on-going.  It feels like a big hammer, but I'm not convinced that we
> > will see a lot of contention on it.
> 
> Regarding that last topic, this could become a fairly contended lock on
> a switch with lots (e.g: > 5-6) of built-in PHYs, all being polled
> (which is usually the case right now). One would expect that the polling
> should be limited to 2 BMSR reads to minimize the bus utilization.

Hi Florian

In this case, we probably are not doing pages reads, just normal
reads. So there should not be any more contention than there already
is.

	Andrew