netdev - Re: [net-next: PATCH 0/8] Armada 7k/8k PP2 ACPI support

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Message-ID: <CAPv3WKeebw_FG8DAb5gkG=fB9W9pP9Fy3eD7KoDDASGQGtPeaA@mail.gmail.com>
Date:   Wed, 3 Jan 2018 14:36:22 +0100
From:   Marcin Wojtas <mw@...ihalf.com>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Graeme Gregory <graeme.gregory@...aro.org>,
        Ard Biesheuvel <ard.biesheuvel@...aro.org>,
        "linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "<netdev@...r.kernel.org>" <netdev@...r.kernel.org>,
        "David S. Miller" <davem@...emloft.net>,
        Russell King - ARM Linux <linux@....linux.org.uk>,
        "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Antoine Ténart <antoine.tenart@...e-electrons.com>,
        Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
        Gregory CLEMENT <gregory.clement@...e-electrons.com>,
        Ezequiel Garcia <ezequiel.garcia@...e-electrons.com>,
        Nadav Haklai <nadavh@...vell.com>,
        Neta Zur Hershkovits <neta@...vell.com>,
        Grzegorz Jaszczyk <jaz@...ihalf.com>,
        Tomasz Nowicki <tn@...ihalf.com>
Subject: Re: [net-next: PATCH 0/8] Armada 7k/8k PP2 ACPI support

2018-01-03 14:33 GMT+01:00 Andrew Lunn <andrew@...n.ch>:
> On Wed, Jan 03, 2018 at 02:13:09PM +0100, Marcin Wojtas wrote:
>> Hi Andrew,
>>
>> 2018-01-03 13:47 GMT+01:00 Andrew Lunn <andrew@...n.ch>:
>> >> I already agreed with 'reg' being awkward in the later emails.
>> >> Wouldn't _ADR be more appropriate to specify PHY address on MDIO bus?
>> >
>> > Also, how do you specify which MDIO bus the PHY is on. To fully
>> > specify a PHY, you need both bits of information.
>> >
>> > In DT, the phy-handle phandle can point to any PHY anywhere in the
>> > system. This is particularly important when a Ethernet device has two
>> > MDIO busses.
>> >
>>
>> For now, my local MDIO bus description is pretty DT-like, i.e. master
>> bus with children PHYs:
>>         Device (MDIO)
>>         {
>>             Name (_HID, "MRVL0100")                             //
>> _HID: Hardware ID
>>             Name (_UID, 0x00)                                   //
>> _UID: Unique ID
>>             Name (_CRS, ResourceTemplate ()
>>             {
>>                 Memory32Fixed (ReadWrite,
>>                     0xf212a200,                                 // Address Base
>>                     0x00000010,                                 //
>> Address Length
>>                     )
>>             })
>>             Device (GPHY)
>>             {
>>               Name (_ADR, 0x0)
>>             }
>>         }
>>
>>         Device (XSMI)
>>         {
>>             Name (_HID, "MRVL0101")                             //
>> _HID: Hardware ID
>>             Name (_UID, 0x00)                                   //
>> _UID: Unique ID
>>             Name (_CRS, ResourceTemplate ()
>>             {
>>                 Memory32Fixed (ReadWrite,
>>                     0xf212a600,                                 // Address Base
>>                     0x00000010,                                 //
>> Address Length
>>                     )
>>             })
>>             Device (PHY0)
>>             {
>>               Name (_ADR, 0x0)
>>               Name (_CID, "ethernet-phy-ieee802.3-c45")
>>             }
>>             Device (PHY8)
>>             {
>>               Name (_ADR, 0x8)
>>               Name (_CID, "ethernet-phy-ieee802.3-c45")
>>             }
>>         }
>>
>> Which is referenced in the port's node:
>>
>> Package () { "phy", Package (){\_SB.XSMI.PHY0}},
>
> Hi Marcin
>
> This reference looks good, giving both the bus and the PHY on the bus.
>
> I assume you can use references like this within the Device (PHY8)
> node?

Yes.

> You need to be able to reference a GPIO used for resetting the
> PHY. And you also need to reference a GPIO at the Device (MDIO) level
> for resetting all the PHYs on the MDIO bus.
>

Yes, for full support of PHYs the GPIO must be supported, as well as
the PHY's IRQs.

Best regards,
Marcin